%Introduction

The demise of Dennard scaling has motivated chip designers to invest
in both architectural and microarchitectural heterogeneity in order to
reap the potential energy-efficiency benefits of computational
specialization and gain access to a larger dynamic range of
power-performance tradeoffs. State of the art smart-phones, the
personal computing platform for much of the world, exemplify this
trend. High-end smart-phones integrate a multi-core arrangement of
both aggressive and lightweight general purpose processors alongside a
GPU and a collection of dedicated accelerators, all in a single chip.

With the maturation of 3D stacking techniques, heterogeneity in the
technology used to implement processing elements can also be
considered. There exist a number of alternatives to CMOS technology
that offer different power-performance tradeoffs when each is run in
their preferred operational regime. One common feature of the key
near-term contenders (e.g. HTFETS) for supplanting CMOS in terms of
energy efficiency, however, is that these CMOS alternatives tend to
offer improved efficiency at the cost of degraded latency
characteristics~\cite{nikonov-benchmarking}. In this paper, we focus on
Heterojunction Tunnel FETs (TFETs)~\cite{Lu-tfet-scaling} as the CMOS
alternative, as their expected performance, especially at future technology generations, is more similar to that of
high-performance CMOS than many other candidates.

While per-operation latency expectations in a given TFET-based
processing element will be inferior, there is the potential to offer
superior throughput within the same power or thermal budget by
employing more TFET processing elements in parallel and exploiting
their superior efficiency. As with other applications of this standard
formulation of trading between parallel efficiency and serial latency,
the key questions are whether there is both sufficient parallelism to
exploit and sufficiently low overheads in extracting the application's
parallelism to provide a crossover point between a CMOS and TFET
implementation, and whether that crossover point exists at a plausible 
point in the design space.

In this paper, we consider the impacts of device heterogeneity across
three forms of parallelism: instruction-level(ILP), thread-level(TLP),
and data-level(DLP). We show that workloads exist that favor both CMOS
and TFET designs at both the ILP and TLP levels, warranting
heterogeneous solutions featuring both CMOS and TFET cores. For
applications that scale well in TLP, not only are TFET cores
preferred, but we show that TFETs also open up new portions of the
<core frequency,core count> design space that were not previously thermally
viable. Further, we examine DLP in the form of implementing
data-parallel accelerators in both a CMOS and TFET standard cell
library and show that the area-performance tradeoff is a reasonable
one for scaling TFET-based accelerators up to the performance of their
CMOS counterparts. In contrast to the benefits seen in our exploration
of ILP and TLP for employing both CMOS and TFET-based cores
simultaneously, the case for implementing the highly-parallel, and
thus TFET-amenable, accelerators in both technologies in one design is
less clear.


% LocalWords:  microarchitectural tradeoffs multi GPU 3D CMOS HTFETS FETs TFETS
% LocalWords:  Heterojunction TFET ILP TLP DLP TFETs tradeoff
